Buffer system



May 19, 1970 P. N. ARMSTRONG BUFFER SYSTEM 9 Sheets-Sheet 1 Filed Junel1, 1969 N NNMMIWIKQQQN ukwuiwlwlvwx May 19, 1970 P. N. ARMSTRONG BUFFERSYSTEM N N d .1, f EL m E NQ @am W. 1% n. 1 m QN QQAS NNN Pw Nm ww S 9ww l f w. www QQN 5 r ww 9 n. 1 N 1, wmN N N MQ .QR u WSW@ n i k n lu...M I w u WWK m xibkv www@ May 19, 1970 P. N. ARMsrRoNG BUFFER SYSTEM 9Sheets-Sheet 5 Filed June 1l, 1969 5 ffm-ffl 51;)

www W Mm n 2a r WZ A. ,w

May 19, 1970 P. N. ARMSTRONG BUFFER SYSTEM 9 Sheets-Sheet 4 F'iled Junell, 1969 ,4free/veg:

May 19, 1970 P. N. ARMSTRONG BUFFER SYSTEM 9 Sheets-Sheet 5 Filed June1l, 1969 BNG @MSE

NN kid May 19, 1970 P. N. ARMsTRoNG BUFFER SYSTEM Filed June ll, 1969 9Sheets-Sheet 6 May 19, 1970 P. N. ARMSTRONG 3,513,448

BUFFER SYSTEM May 19, 1970 A P. N. ARMsTRoNG 3,513,448

BUFFER SYSTEM Filed June 1l, 1969 9 Sheets-Sheet s 1g-W10 640 afm/fl)Arran/V07 May 19, 1970 P. N. ARMsYTRoNG 3,513,443

BUFFER SYSTEM Filed June 11, 1969 9 Sheets-Sheet 9 k. E* Q* *s i L x )QQw n n 3x N N y, w w Q Q 5 Q S S Q il* LUN BQ Q 53 w b HT i i 's Q \1- Wt Q Q Q \l w w E l l i *G5* Wray/50A. Q f la; WM/'o Afr/f on @3 "Q +S*ik w United States Patent O 3,513,448 BUFFER SYSTEM Philip N. Armstrong,1733 Keegan Way, Santa Ana, Calif. 92705 Continuation-impart ofapplication Ser. No. 610,666, Jan. 20, 1967. This application June 1l,1969, Ser. No. 832,333

Int. Cl. 606k 17/00 U.S. Cl. 340-1725 11 Claims ABSTRACT 0F THEDISCLOSURE The invention relates to a buffer data storage system of thedynamic circulating type for binary data in a process ing system. Datais introduced serially to the input and may be derived serially from theoutput at any time on a first-in, first-out basis.

This application is a continuation-in-part of copending application Ser.No. 610,666, tiled Jan. 20, 1967 which has now been abandoned.

BACKGROUND OF THE INVENTION SUMMARY OF THE INVENTION The improved buiierdata storage apparatus of the invention is of the dynamic circulatingtype, in which data is introduced at the input thereof as a serialstream of binary multi-bit records; and from which the data may bederived at the output thereof, when required, and in exactly the samerecord order in which it was introduced.

A feature of the system is that it exhibits overall variable delay linecharacteristics, in that the first record of any number of recordsserially introduced into the buiier can be recovered within one recordtime after it has been entered. This means that the buffer storageapparatus of the invention has a tremendous flexibility, in that it canbe used to store several or a vast multiplicity of records, withoutsacrilice in recovery time, regardless of how few records may beintroduced into the buffer for any particular operation.

The improved buffer to be described has the capabilities of magnetictape data correlating apparatus in which the tape is stored between awrite and a read station; the amount of stored tape depending upon thenumber of record times desired between writing and reading. The bufferof the invention is for use generally in the autocorrelation of data.

As an additional feature, records may be recovered serially from theoutput of the buffer store apparatus of the invention concurrently withthe serial introduction of other records into the buffer.

A primary object of the invention is to provide an improved, simple andrelatively inexpensive buffer storage apparatus having the featuresreferred to above.

Another object of the invention is to provide such an improved buterstorage apparatus of which a particular constructed embodiment iscapable of storing with a minimum of access time, any number of recordsup to a predetermined maximum; and which is conceived so that itsembodiments may be constructed to handle any desired maximum number ofrecords, as required by any particular installation.

3,513,448 Patented May 19, 1970 As will become evident as thedescription proceeds, the improved buffer storage apparatus and systemof the invention is capable of receiving and storing data so long as itis not full. Any data record may be introduced into the buffer system ina maximum of two record times. That is, n records can be seriallyintroduced into the buiier of the invention in not more than n+1 recordtimes. Also, the introduction of data records into the butter can beinterrupted and recommenced at any record time, and each suchinterruption may continue for any desired number of record times.

Moreover, and as mentioned above, a serial stream of records may bederived from the output of the buffer at any record time, in excess ofone, after a rst record has been fed into the system. Not more thanmi-l-l record times are required to recover m records from the buffer,and this output operation can be commenced immediately after the firstrecord is fed into the buffer. Moreover, the output operation can becommenced at any time, and can be interrupted after it has beencommenced at any record time, and the interruption can continue for anydesired number of record times.

The features of the invention which are believed to be new are set forthwith particularity in the claims. The invention itself, however,together with further objects and advantages may best be understood byreference to the following specication, when taken in conjunction withthe accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates the binary bitcomposition of the various data and blank records utilized in the systemof the invention;

FIG. 2 is a block diagram of a buffer storage apparatus constructed inaccordance with one embodiment of the invention;

FIGS. 3-5 are logic circuit diagrams of the various components which goto make up the butter storage apparatus of FIG. 2;

FIG. 6 is a block diagram showing the connections between the variouslogic circuits;

FIG. 7 is a schematic showing of the manner in which records input intothe system circulate therein, so as to be available at the output insame order as which they were introduced;

FIG. 8 is a block diagram of a butter storage apparatus construction inaccordance with a second embodiment of the invention;

FIG. 9 is a block diagram of a buffer storage system constructed inaccordance with another embodiment; and

FIGS. 10-12 are logic diagrams of circuitry included in the embodimentof FIG. 9.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS As mentioned above,the `binary data which is fed into the buffer store apparatus and systemof the invention for storage therein until needed is divided into aplurality of individual records, each record being composed of the samenumber of binary bits, and each including a two-bit control field. Thedata record, as shown in FIG. 1, includes a multi-bit data field, as`well as a two-bit control field. The data field may be made up of anyselected number of binary bits, for example, from one hundred (or less)to many thousand. When the indicated control bit X :1, the indication isthat the record is actually a data record. Then, the control bit Y maybe coded, as shown in FIG. 1I to designate an ordinary data record (D)(Y=O), or a distinguished data record (Dl) (Y=1). The significance ofthese two types of data records will be described subsequently. Eachrecord is fed into the system at successive bit times t1, t2, la. Thecontrol bit Y occurs at t1 bit time and the control bit X occurs at t2bit time.

Likewise, with respect to the blank record, the X-bit in the controlfield is made equal to zero, Then, the Y-bit may be coded, as shown, sothat when Y=0, an ordinary blank record (B) is indicated; whereas, whenY=1 a distinguished blank record (B*) is indicated. These data and blankrecords are described in more detail in the aforesaid patents.

The construction of the buffer determines the size of the record whichit can handle. However, the buffer construction can be tailored tohandle records of any size up to, for example, several thousand bits.However, each record must include at least four bits, and it iscontemplated that for most applications, records of 100 data bits ormore would be accommodated. However, it will become evident that whenthe buffer of the invention is cornbined with a conventional buffer, thedata blocks may indeed be three or four bits long.

As will be described in detail in conjunction with the block diagram ofFIG. 2, the buffer storage apparatus of the invention includes a seriesof serial memory elements of various record lengths. These memoryelements are in the form of delay lines, or their equivalent, such asdescribed in the aforesaid patents. Data is introduced into one end ofeach such delay line memory element as a serial record stream, and itemerges from the other end at a later record time, as determined by theetfective length of the particular delay line memory element.

It should be noted that the term record time as used herein denotes thetime required to pass one record, of the type shown in FIG. 1, on aserial bit-by-bit basis into any one of the aforesaid delay line memoryelements.

The number of serial delay line memory elements included in theapparatus is, for example, in the following progessions: l, 2. 4 2, 2,2n1, 2-2 1 (if n is even); and l, 2, 4 211A, 2, 2n1 1 (if n is odd). Inthe above progressions, the numerals represent the lengths of thevarious memory elements in terms of records. However, if the data is tobe taken out of the buffer in one long series of data words, with nohiatus, there is no need for the lines represented by the upper half ofeach progression. Likewise, if the data is to be fed into the butler inone long series of words, with no interruptions, there is no need forthe lines represented by the lower half of each progression.

A block representation of the buffer store, representing one embodimentof the invention, is shown in FIG. 2. The store includes a rst group ofcircuits, represented by the blocks So-SB, and a second group ofcircuits represented by the blocks S'l-S'.

All the circuits mentioned iu the preceding paragraph are the same, andeach may be composed of the logic circuit details shown in FIG. 4 underthe designation Si, as will be described in detail subsequently herein.The circuit S, serves to exchange its two inputs, under certainconditions, as will be described.

The block representation of FIG. 2 also includes a plurality of circuitsrepresented by the blocks Al-A. All these circuits are essentially thesame, except for certain differences to be described. The logic circuitdetails which make up the individual circuits are shown in FIG. 3 underthe designation A1, as will be described in detail subsequently in thepresent specification.

The circuit A, determines whether any particular record output of acorresponding memory element is a rst or distinguished record (D* or B*)and is, therefore, eligible for exchange in the associated circuit S1with the output of another memory element.

The block representation of FIG. 2 also includes a plurality of circuitsrepresented by the blocks Bl-B. All these latter circuits are the same,and the logic details of the individual circuits are shown in FIG. 5,under the designation B1. This latter circuit, likewise, will bediscussed in detail in the ensuing description.

The circuit B, serves to label the records passed through it to thecorresponding one of the memory elements. For example, if a particularrecord is a first record, it must be distinguished, so that a l is leftinthe Y control bit position. lf, on the other hand, a particular recordpassed through the circuit B1 is not a first record, a 0 is placed inthe Y control bit position.

It will be appreciated that data records of the type illustrated, forexample, in FIG. lA are fed into the SyS- tem in a serial stream along aline 10, from any data source, or sources. These data records are suchthat their control fields designate distinguished data (D*) (X Y). Aspointed out previously, this stream may be interrupted after any numberof records have been fed into the system, and can be subsequentlyrecommenced after any number of record times have elapsed. The line 10connects, as shown, with one of the input terminals ibs of the circuitS6.

As mentioned above, the system of the invention is capable of storingthe stream of records introduced into it along the line 10, and of thenproducing the stream of records in the same order, whenever desired.Also, the system of the invention is capable of producing the firstrecord of the input stream at its output in not more than one recordtime if so desired. The records are caused to appear at the output line11 of the buffer system by the introduction of distinguished blankrecords (B*), of the type shown in FIG. 1B, along the line 12, whichline connects with the input terminal a0 of the circuit S0. At all othertimes, blank reco-rds (B) (LY-) are introduced to the system along theline 12. The blank records appear on the output line 11 of the bufferand serve to hold the data records in the system until the outputoperation is commenced. The blank records B are also used for otherpurposes, as will become evident as the description proceeds. Thisaction is similar to that described in the aforesaid patents.

The buffer system of FIG. 2 includes a series of delay line memoryelements, these being designated in the illustrated embodiments as `14,16, 18, 20, 22 and 24. The memory elements have record lengths selectedin accordance with the formula previously set out herein. In theillustrated example, for example, the memory elements are 1, 2, 4, 4, 2,1 record lengths respectively.

It will be appreciated that the memory elements 14, 16, 18, 20, 22 and24 may be in the form of actual delay lines, of any particular knownconstruction. Also, these memory elements may be constituted by writingthe records on individual tracks of a memo-ry disc, tape or drum, and ofsubsequently reading the records at the predetermined number of recordtimes, so as to constitute the desired elective delay, or storage time,in the individual memory elements. Similarly, they may be composed ofmagnetic core memories of conventional construction with appropriatecapacities, or suitably equipped magnetic tape equipment. Suitablememory elements for this purpose are shown and described, for example,in Armstrong Pats. 3,015,089 and 3,399,383.

As shown, the outputs #1-#6 of the respective circuits Bl-B circulateback to the inputs of respective ones of the memory elements 14, 16, 18,20', 22 and 24.

The outputs Ll-Ls (Li) of the respective memory elements are introducedto the respective circuits A1-A (A1). The circuits Al-A are connected tothe input terminals of the circuits So-Se (Si), in the manner shown, andthese latter circuits are interconnected with each other, and with thecircuits S'1S (SQ) in the illustrated chain relationship. The circuitsS'l-SG are connected to respective ones of the circuits Bl-BE. Whendistinguished blank records (B*) are introduced along the line 12 intothe system, the data records are derived on the line 11 which isconnected to the output terminal co of the circuit S0. At the same time,blank records appear on the line 32 which is connected to the outputterminal d'6 of the circuit S'e.

As mentioned above, the logic details of the circuit A1 are shown inFIG. 3. This circuit is used to cause an output record from thecorresponding memory elements 14, 16, 18, 20, 22 or 24 (designatedgenerally as L1) to be distinguished (D* or B*) under the propercircumstances, so that it will be eligible for exchange with the outputof another memory element. On the other hand, the circuit A1 removes the1 from the record (B* or Bi) from its corresponding memory element ifthe proper circumstances are not fullilled.

For example, a data record (D) coming out of the corresponding memoryelement (L1) is caused to become D* by the A1 circuit if there is nodistinguished record (D*) in the memory element as designated by thelogic term (511') The circuit A1 also serves to cause a blank record (B)received from the corresponding memory element (L1) to be distinguished(B*) when there are no distinguished blank records (B*) in the memoryelement, and there is data in the corresponding memory element asdesignated by the logic term (D*1-*1).

In addition, if a particular circuit A1 is in the upper half of thesystem and if all the memory elements between and n-i--l are empty (N1);then if a distinguished blank record (B*) is detected by a circuit A1,then any blank record (B) detected by A1 1 and A11 1+1 is distinguished(B*). If A1 is in the lower half of the system and a distinguished blankrecord (B*) is detected in A11 1+1, a blank record (B) in A11 1+2 isdistinguished (B*) if A11 1+2 has no B* (11 1+2).

The circuit for accomplishing the above is shown as A1 in FIG. 3. Thecircuit A1 includes a pair of ip-ops T11 and T12. These are connected asa two-bit shift register. The input L1, which is derived from theassociated memory elements 14, 16, 18, 20, 22 or 24, is introduced tothe set input terminal S of the ilip-flop T11, and through an inverter100 to the reset input terminal R of that Hip-flop. The T11 output fromthe ip-op T11 is applied to the set input terminal of the hip-flop T12,and through an inverter 102 to the reset input terminal.

It will be appreciated that as the input L1 is shifted into the circuitof FIG. 3, it passes in a bit-by-bit sequence through the two iip-opsT11 and T111 of the shift register. The bit timing is assumed to be suchthat at t1 bit time, the Y bit of the data or blank record in FIG. l isin the T111 flipdlop, and the X bit of the data or blank record is inthe T11 flip-Hop. The term tc is a bit timing term which occurs duringeach successive bit time, with the exception of t1. Therefore, t,1=1.

The ip-ops in the circuit of FIG. 3 are identified as T11 and T12 so asto indicate that similar tlip-ops occur in each of the various A1circuits. The set output terminal T12 of the ip-tlop T12 is connected toan and gate 104, as is the term tc. It will be appreciated, therefore,that as the record L1 is stepped into the circuit A1, all the bits ofthe record are passed unchanged through the and gate 104, and through anor gate 106 to the output terminal of the circuit, with the exception ofthe Y, or first bit.

The circuit A1 either serves to make the first bit, or Y bit, a l undercertain circumstances, so that the corresponding data or blank recordmay be distinguished, or to make it a under certain circumstances, sothat the corresponding distinguished blank or data record (B* or D*) maybe returned to its undistinguished state (B or D).

The circuit A1 also includes a ipdiop D*1. The tlipop is set when adistinguished data record (D*) is placed in the corresponding memoryelement L1, so that the llipop D*1 indicates the presence of adistinguished 6 data record (D*) in the associated memory element L1.The ip-op D*1 is set by terms t1R111 from the circuit B1 (to bedescribed in conjunction with FIG. 5) which are introduced to the setinput terminal through an an gate 108. The flip-dop D*1 is reset when adistinguished record (D*) is read from the associated memory element L1this being achieved by the term T11'I`1-,1 and t1 which are introducedto the reset input terminal of the flip-flop D*1 through an and gate110.

The circuit A1 also includes a tlip-op B*1. This latter ip-tlop is setby the terms r11-t11 and R21 which are also derived from the B1 circuitof FIG. 5, and are introduced to the set input terminal of the llip-tlopB*1 through an and gate 112. The setting of the Hip-flop B*1 occurs whena distinguished blank record B* is placed in the associated memoryelement L1. That is, the flip-Hop B'11 indicates the presence of adistinguished blank record B* in the associated memory element L1.

The flip-flop B*1 is reset in the circuit A1 when a distinguished blankrecord B* passes out from the associated memory element L1 and throughthe A1 circuit. This resetting of the B*1 ip-op is achieved from theoutput of an and gate 114, the terms T11 and T12, and t1 beingintroduced to the an gate.

The A1 circuit of FIG. 3 also includes a ip-ilop N1. The flip-Hop N1 isset to indicate the absence of data in the corresponding memory elementL1.

Whenever a data record is passed from the circuit B1 of FIG. 5 to the L1memory element, the ip-op N1 is reset by the terms R11 and t1, which areintroduced to the reset input terminal of the llip-flop N1 through anand gate 116. The flip-tlop N1 is set by the presence of an ordinaryblank record (B) in the memory element L1, and when the D*1 ip-op isreset, which indicates that no data record has as yet been placed inthat memory element L1. The setting of the flip-flop N1 is achievedthrough an an gate 1118, the terms )'1*, T21, T11 and and t1 beingintroduced to the and gate.

In order for the circuit A1 to perform all the functions describedabove, an additional group of and gates 120, 122, 124 and 126 areincluded in the circuit. These and" gates are all connected through anor" gate 128 to an and gate 130. The term t1 is applied to the and" gate130, and that and gate is connected to the output terminal through theor gate 106. The circuit also includes an and gate 127 which also isconnected to the or gate 128. The term 1.111, N1 and t1 are bothintroduced to the and gate 127.

The terms 511 and T11 are applied to the and gate 120. The terms D1 and11', together with the term T11 are introduced to the and" gate 122. Theterms N11 1+2, N11-H3 N1, '11 1+1, N 111 and T1111+1 are all applied tothe and gate 124. The terms T11, T*1 1, it-*1 1 and T11r1 are allapplied to the and gate 126.

The output term L1 of the circuit A1 can be expressed by the followinglogic equation:

In the above equation, the term L1,1 represents the data or blank recordwhich is passed by the T1 network, with all the bits unchanged, with theexception of the first or Y bit (FIG. 1), which may or may not bealtered, in accordance with the remaining terms of the equation. Becausethe Y bit occurs at t1 time, all the remaining terms in the equation arequalied by the i1 term.

With respect to D1* -T11 this term indicates that a data record is beingread out of the corresponding memory element L1, and that there is nodistinguished data record (D*) in the memory element. This data recordis to be distinguished by A1, so that its Y bit is made into a l by theterm in question.

Likewise, the term D,",""`T,l represents that a bank record is beingread out of the corresponding memory element 1. that there is datarecord in the corresponding memory element, and that there is nodistinguished blank record in the memory element. The operation of thesystem requires that such a blank record (B) be distinguished (B*) Theremaining terms in the above equation fulll the conditions describedabove, whereby the blank records out of certain empty lines aredistinguished.

As mentioned above, all of the circuits S,S and S,-S6 are identical.These circuits may each be represented by the circuit S, of FIG. 4. 'Ihecircuit S, acts on the inputs applied to its input terminals a and b, sothat these inputs appear either in the same position at the outputterminals c and d, or in an exchanged position at the output terminals.

The circuit S, will make the exchange if a distinguished blank record(B*) is applied to the a input terminal,

and a distinguished data record (D*) is applied to the b input terminal,if further conditions are met.

For example, it is also required that a D* data record will pass up thesystem past any empty memory element. For this purpose, the S, circuitis made to exchange if a D* record from the memory element L, is appliedto its input terminal b, and the corresponding memory element (L,)connected to the a input terminal is empty (N1). However, a B* must beencountered from the memory element (L,) or the corresponding circuitS', will return the D* record to its original memory element (L, byfailing to exchange the record D*.

The circuit S, includes a p-op E,. This is the exchange tiip-flop, andit is set if the inputs applied to the terminals a and b are to beexchanged. The ip-op E, is set at the beginning of each record time, andif the Hipop remains set throughout the record time, the exchange ismade. However, if the above-stated conditions do not exist, the ilip-opis reset. The term introduced to the ilip-iiop E, to reset the ip-op is:tlL't'z-l-'i-ilad-'ifx-l-Z'i-i'f1] The input terminal a is connected toan and" gate 200 which, in turn, is connected through an or gate 202 tothe output terminal c. The input terminal b, on the other hand, isconnected to an and gate 204 which, in turn, is connected through an orgate 208 to the output terminal d. The term T, is also introduced to theand gate 200, and the term is also applied to the and gate 204.

The input terminal a is also connected to an and gate 212. The latterand gate is connected to the or gate 208. The term E, is applied to theand gate 212. The input terminal b is also connected to a further "andgate 220, as in the term E,. The and gate 220 is connected to the orgate 202.

It will be appreciated that so long as the flip-op E, is reset (E), theinput at the terminal a will pass through the and gate 200 through theor gate 202 to the output terminal c. At the same time, the input at theinput terminal b will pass through the and gate 204 and through the orgate 208 to the output terminal d.

Conversely, when the ip-op E, is Set, the input at the input terminal bpasses through the and gate 220 and through the or gate 202 to theoutput terminal c; and the input at the input terminal a passes throughthe and gate 212 and through the or gate 208 to the output terminal d.Therefore, an exchange is made.

The circuit S, of FIG. 2 may be similar to the circuit S, describedabove, except that its logic may be simplified so that an exchange ismade only when a B* record is applied to its input terminal no and a D*record is applied to its input terminal bo. That is, the secondresetting term of the Hip-flop Eo is omitted.

The circuit B,B6 are identical, and these circuits are represented bythe circuits B, in FIG. 5. The circuit B, serves to append a to the Dand B records, under certain conditions, and it also controls thesetting of the D*, and Bl, flip-ops in the A, circuit of FIG. 3, and theN, flip-flop in the A, circuit. In addition, the output of the circuitB, may have a removed, if the conditions to be described are notfulfilled. The circuit includes two flip-hops R,l and R2i which areconnected as a shift register.

The output of the circuit B, may be expressed as The N, flip-dop isreset when data passes from the output of the B, circuit (L",) to thecorresponding memory element L,. The data flip-tiop Di, is set when adistinguished data record appears at the output of the B, circuit (L",)and is passed to the corresponding memory element L,. Finally, theflip-Hop B*, is set when a distinguished blank record appears at theoutput of the circuit B, and is passed to the corresponding memoryelement L,.

The equation given above for the output L'", is implemented in thecircuit of FIG. 5 by a series of and" gates 300, 302, 304, 306, 308, 310and 311, and a corresponding series of or gates 312, 314, 316 and 318.

The Hip-Hops R,x and R2i are connected as a two-bit shift register asmentioned above. The input terminal x is connected to the set inputterminal S of the iiip-op Rf, and through an inverter 330 to the resetinput terminal R of that iiip-op. The input L, is introduced to theinput terminal x. The output terminal Rli of the flip-Hop R,i isconnected to the set input terminal of the ip-op R2 and through aninverter 334 to the reset input terminal of that flip-flop.

The terms t, and R,l are applied to the and gate 116 as described inconjunction with FIG. 3 to provide a reset term for the flip-Hop N, inthe circuit A, of FIG. 3. The terms t, and R2i are applied to the andgate 108 as described in conjunction with FIG. 3 to provide the settingterm for the flip-flop D*, of the circuit A, of FIG. 3. Finally, theterms R21 and BJ and t, are applied to the and gate 112 as described inconjunction with FIG. 3 to provide the setting term `for the flip-flopB*,.

It will he noted from the circuit of FIG. 5, that at all other bittimes, except t, time, the data L", passes through the ip-op R andthrough the and gate 300 and or gate 316 to the output terminal, whereit appears at the output data L"',. That is, at all times except t, bittime, each data or blank record is passed through the circuit B, and iscirculated `back to the corresponding memory element L,.

The circuit B, of FIG. 5 operates on the Y bit (FIG. 1) of the data orblank record, so as to make the bit a 1, under certain conditions, asexpressed above.

That is, if the associated memory element L, is empty (N,), and thus dodata could have been exchanged in the corresponding exchange circuit S,during the preceding record time; or if there is no distinguished record(D*) in the corresponding memory element, and no exchanges were made ateither the corresponding S, or S', circuit (that is 7a2-PE1), the datarecord passing through the circuit B, should be distinguished, asindicated by the corresponding terms in the above equation.

Moreover, if the record passing through the B, circuit is a B record(B1), then it should receive a if there is no B* record (BH) in thecorresponding memory element (L,), and the memory element contains dataLikewise, the blank record B should receive a if the input to the nextlonger line is a distinguished blank record, as indicated by the term:,lRll-l. It is to be noted that the term ri 1 is used to indicate t1bit leaving the B, circuit for the next longer memory element at t1 bittime.

The remaining condition under which a is applied to a record by the B1circuit is one in which all memory elements between L, and I. 1+2 areempty (Nn 1+2, Nn x+3 N1), and a B* is to be placed in the Ln 1+1indicated by Rlnrstl, El, and NBA and B* 1+1. Therefore, if there were amemory element above L1 1 with a B* output, B* would pass over the emptyline. If no Am of line LH has a B* output, lbut only a D* or B output,the D* should return to its original line. An undistinguished blankrecord (B) is changed to a distinguished record (B*) in B1 if the lineL, contains no B* record, and contains data (l). If a line contains adistinguished data record (D*), the fiip-op D*1 is set, of course.

The fragmentary block diagram of FIG. 6 shows how the differentcircuits, described above, are interconnected in order to carry out theconcepts of the invention.

An example of the operation of the buffer system is shown in FIG. 7. InFIG. 7, successive steps are represented during which data records (D*)are fed into the system, with certain interruptions to be described. Itis to be understood, that the successive steps of the example of FIG. 3are assumed to occur at successive record times. In step one of FIG. 7,all the memory elements are empty (N1), and there are no distinguishedrecords of any type in any of the memory elements.

In step two, it is assumed that a first data record, designated 1 is fedinto the system on the data input line 10 in FIG. 2. At the same time, ablank record B is fed into the system on the blank line 12, to retainthe data record 1* in the system.

As mentioned above, the input records are distinguished (D*) as they arefed into the system. This is achieved by any appropriate circuit (notshown). Therefore, the input y record 1 is a D* record 1*, and itfulfills the condition so that ir may be exchanged by the circuits S8,S5, S4, S3, S2, S, to be set in the #1 memory element L1, as shown.Under these conditions, there are no distinguished blank records (B*)placed in any of the memory elements.

At step three, it is assumed that a second data record, designated (2*)is fed into the system. At the same time, the blank Output from the L2memory element is distinguished (B*) in the circuit A2, because theconditions are fulfilled.

It is assumed that during step four, the next record time, no datarecord is fed into the machine. It will be understood, of course, thatduring each record time, a blank record (B) is fed into the machine online 12 of FIG. 2, so as to hold the data records in the buffer system.

During the conditions of step four, the `B* record is placed in thememory element L2 because the conditions El, B*2 and g are met in thecircuit B2 so that the gate 304 is enabled. Also, a B* record is placedin L5 (L6 2+1) because the term 2'N3'N4-N5B*2T15512 is satisfied.

During the next record time, as shown by step five, is is assumed thatthe third record 3* is fed into the machine.

Here, the record 3 is placed in the memory element L8, as shown, becausethere is no B* output from any of the other elements. It will beobserved that the information in the memory elements L1 and L2 circulatein steps four and five, because they do not fulfill any conditions forexchange in their associated exchange circuits.

During the next record time, as shown, by step six in FIG. 7, the datarecord 4* is fed into the system on the input line 10. During thislatter operation, the conditions are such that the data record 3* istransferred up to the memory element L2 and the data record 4* isretained in the memory element L6. During the operation, the data record3 loses its in the circuit B2, because there is a distinguished datarecord in the L2 memory element D'lz.

At step seven, no further record is introduced into the system. The datarecord 4* is transferred up to L3, and retains its because it is thefirst data record to be placed in the memory element L3. Before the datarecord 4* is placed in the memory element L3, the 2* record was outputfrom the circuit A2. Hence, the condition [02*B'2 *T13T121 existed inthe circuit A3 to enable the gate 126 of FIG. 3, so that there was a B*output from the circuit A3 which permitted the exchange to be made sothat the 4* data record could be placed in the memory element L3.

In the next record time, step eight in FIG. 7, again, no further datarecord was placed in the system. During these conditions, and as shown,a B* record is placed in the L3 memory element since the term ELITE-N3is satisfied. Also, a distinguished blank record B* is placed in thememory element L4 because N1 4+2-364+1R`31I541 is satisfied. Likewise, ablank distinguished record B* is placed in the memory element L5 becausethe term T51-B*5-N5't14 is satisfied.

Likewise, and as shown, a B* is placed in the memory element L6. In stepnine, still no further data record is introduced into the machine, andthe illustrated condition obtains. This also applies to step ten. Itwill be noted in the latter step, that a B* is inserted in the memoryelements L4, L5 and L6 because there is a B*, in each instance, in thenext higher line.

Likewise, in steps eleven and twelve, no further data is introduced intothe machine, and the illustrated conditions occur. At step thirteen, thedata record S* is introduced; and at step fourteen the data record 6* isintroduced. No data is introduced during the word time corresponding tostep fifteen, or in any other of the following illustrated steps.

During step sixteen, the data record 5 does not have a when inserted inthe memory element L3, because of the presence of a distinguished datarecord 4* in that memory element. Also, there is no distinguished blankrecord B* in the memory element L4, because 3-13N4R1 is not satisfied.

In step eighteen, it is assumed that the data record 1* was removed fromthe system. This is achieved by introducing a B* blank on the line 12 ofFIG. 2, so that it will exchange with the data record 1* in the exchangecircuit S0, and appear at the data output line 11 in FIG. 2. It will benoted in step nineteen that the conditions are such that there are nodistinguished data records in the memory element L2, or in any other ofthe elements of the system.

In like manner, the system can be controlled through additional steps asdata is fed into the buffer on line 10 of FIG. 2, or removed from thebuffer on line 11.

The invention provides, therefore, an improved buffer storage apparatusin which data may be introduced at the input thereof as a serial streamof binary multi-bit data records.

As described above, the input operation of the data records may beinterrupted at any record time, merely by introducing a blank record (Bor B*) on the input line l0, and the interruption may be continued forany desired number of record times. Also, the output operation may becommenced at any record time during the input operation, after the inputoperation, or during any interruption in the input operation, merely byintroducing a distinguished blank records (B*) rather than an ordinaryblank record (B) on the line 12.

The function of the exchange circuits So-S and S'DS'G is to exhibit thecapabilities of exchanging records from the inputs 10, 12, L'l-L'e, sothat any one of such records may appear at any one of the outputs 11,32, L1-L"6. This function may be achieved by a variety ofinterconnections of the exchange circuits SD-S and S'l-S's, a secondtype of network capable of performing the function being shown in FIG. 8and including a plurality of exchange circuits S, connected as shown,and which indi- 1 1 vidually may be similar to the exchange circuitsSD-S and S'l-S's of FIG. 2.

As described above, the exchange circuits SU-Sm S1Ss are individuallycontrolled so as to exchange their inputs, only if certain conditionsare met. That is the individual exchange circuits will respond to a datarecord input and exchange it with its other input, only if the otherinput is a blank record. If two data records are applied to anyindividual exchange circuit, no exchange is made. Moreover, an exchangeis made between a data record and a blank, only if it is the first datarecord out of a line. The overall control is such that a data outputrecord from any memory element is either returned to the same memoryelement, or if it s the first data record out of the particular memoryelement, it is returned to a higher memory element which exhibitscorresponding blank records.

The exchange circuits S of the embodiment of FIG. 8 may be controlled inthe same manner as described above to perform the same individual andoverall function as the circuits S-S and S1-S6 of FIG. 2.

The embodiment of the invention shown in FIG. 9 is essentially similarto the embodiment of FIG. 8, except that certain changes andmodifications are efectuated whereby the necessary logic circuitry issimplified to a large extent. The embodiment of FIG. 9 may use memoryelements (not shown) similar to those designated 14, 16, 18, 20, 22 and24 in FIG. 2, with the corresponding outputs Ll-Ls (Ll) being connectedrespectively to circuits Al-As (A1), 3S Shown.

As before, the memory elements have records lengths selected inaccordance with the previous formula, and in the illustrated example ofFIG. 9, the record lengths of the memory elements are 1, 2, 4, 4, 2, 1respectively. As before, the memory elements may be in the form ofactual delay lines, or they may be constituted by writing the records onindividual tracks of a memory disc, tape or drum, and of subsequentlyreading the records at predetermined record times later, so as toconstitute the desired effective delay, or storage time, in theindividual memory elements.

Likewise, the circuit of FIG. 9 includes a series of circuits B1-B6(B1)whose outputs are designated Lint-L61" (Lilli) and which are connectedback to the respective inputs of the various memory elements, as in theprevious embodiments.

The outputs L1L6(L,) of the respective memory elements are introduced tothe respective circuits A1-AG(A,) in the circuit of FIG. 9, asmentioned, and these latter circuits are connected to one of the inputterminals of the circuits SS6(S|), in the manner shown, and these lattercircuits are interconnected with each other, and with the additionalcircuits S1-S(S,) in the illustrated chain relationship. One of theoutput terminals of the circuits Sl-S are connected to respective onesof the circuits Bl-B in the system of FIG. 9.

When distinguished blank records (B*) are introduced into the systemalong the line 400, which is connected to the other input terminal ofthe circuit S8, the data records are derived on the line 402 which isconnected to the other output terminal of the circuit S'. This occurswhen data records are introduced into the system along the line 404which is connected to the other input terminal of the circuit S0. At thesame time, the blank records appear on the line 406 which is connectedto the other output terimnal of the circuit S0.

The circuits Aa, A5, A4, A3, A2, A1, are interconnected, as shown, sothat whenever a circuit A1 detects a it serves to introduce a to thedata or blank record then passing through the adjacent circuit A1, aswill be described in greater detail. Likewise, the circuits B-Bl, B-B2,and B4-B3, are interconnected as shown, so that whenever a is removedfrom a record by a particular 12 one of the circuits Bi, a is removedfrom a corresponding record in the other circuit B, to which the firstis connected, as also will be descibed in greater detail.

For purposes of description, it may be assumed that each of the circuitsA1, S, and B1 is equipped with a twobit shift register. The two-bitslabelled X and Y in FIG. l will be referred to in the followingdescription as XA, XS, XB and YA, Ys, YB, depending upon which group ofcircuits is being referred to; and, where necessary, these bits -will bereferred to as XA, XS, XBl and YAi, Ysi, YB" to indicate the bits in thearticular circuits.

For all the circuits A1, S1 and B1, at time to, the first bit of a dataor blank record will be assumed to be an X; at time t, the first bitwill be assumed to be a Y and the second bit will be an X; and at timet2, the first bit will have passed from the circuit, and the second bitwill be assumed to be a Y. In the circuits Ax, a is appended to a datarecord if a data record enters the particular circuit A and itscorresponding memory L, does not contain a (*'d) data record (D*).Likewise, a is appended to a blank record if there is data in thecorresponding line (L1) but no B* blank record, or if a is derived fromthe line AIM.

The aforesaid action of the A, circuit is shown in the logic diagram ofFIG. l0, in which a series of and gates 500, 502, 504 are connected toan or gate 506 which, in turn, is connected to an or gate 508. An andgate 510 is also connected to the or gate 508. The terms lt, XA, and t1,are applied to the and gate 500; the terms Ef, XA, t1 and D*, areapplied to the and gate 502; and the terms 5ft, 2*, A, and the from thenext line A1 are applied to the and gate 504.

The terms applied to the and gate 500 causes a to be appended to a datarecord (t1, XA) if the corresponding memory element does not contain adistinguished data record (Tipi). Likewise, the and gate serves to applya to a blank record (t1, XA) if there is data in the correspondingmemory element (DM), and if there are no distinguished blank records(B*) in the line, as designated by the term The and gate S04 serves toapply a to the output of the A, circuit, if such a is received from thecircuit Am, and under the conditions where a blank record in the circuitA, is undistinguished ('*1, A) and there are no distinguished records inthe corresponding memory element il).

The and gate 510 assures that all records passing through the A, circuitlose their by virtue of the terms i1, YA. However, additional logiccircuitry in the A, circuit, as shown by FIG. 11, and which includes andgates 512 and S14 resets the records to their distinguished condition,when a distinguished record enters the circuit. The data records D, arereset by the and gate S12, due to its input terms XA, YA, t1. Likewise,the blank records are reset by the and gate 514, due to its input termsA, YA, tl.

The circuits S1 and S', are identical, and are similar to thosepreviously described herein. The circuit S, does not change its inputsexcept to exchange them under the conditions prescribed herein. That is,the S1 circuits exchange their inputs only when the input applied to theupper input terminal is a B*, and the input applied to the lower inputterminal is a Di. This also applies to the circuits S,. Otherwise, theinput applied to the upper input terminal is passed to the upper outputterminal, and the input applied to the lower input terminal is passed tothe lower output terminal.

The circuits B1 are shown in logic detail in FIG. 12, and these circuitsinclude a group of and gates 600, 602, 604 and 606 which are connectedto an or gate 608. The output of the or gate is passed through aninverter 610 to an or gate 612. A further or gate 614 is connected tothe or gate 612. The output of the inverter 610 is also connected to a`pair of and gates 616 and 618.

The circuit B1 serves to remove the from a data record if there alreadyis a distinguished data record in the corresponding memory element(Dfi). This is accom plished by the terms Dlf, XB and l, applied to theand" gate 600. The circuit B1 also serves to remove the from adistinguished blank record, if there already is a distinguished blankrecord (Bl) in the corresponding memory element. This is accomplished bythe and gate 604, the terms Bli, B and t1 being applied to the latterand gate.

The circuit B1 also serves to remove the from a distinguished record ifthe record in the particular circuit Bi came from a lower line, and ifthe output of the corresponding memory element Li was a data recordwhich was introduced to a higher line. This is achieved by the and gatek602, and by the terms ii, Bf, E1, t1 and XB, applied to the and" gate602.

The and gate 606 serves to remove the from a blank record, underconditions where the output from the corresponding BD H] circuit isundistinguished (T) where ign/2 if n is odd; and

if n is even. n the other hand, if the output from the correspondingcircuit Bn 1+1 is either a D* or B* record, the output of the circuit Bxis Bl, since the an gate 606 is then disabled. This is accomplished bythe terms B, Bli, ll, t! and applied to the an gate 606.

The output from the or gate 608 is passed through the inverter 610, andthen back to the corresponding memory element L1 through the or gate612. The or gate 614 selves to remove the ("f) of all distinguished dataor blank records applied to the circuit B1. However, the and gate 616resets each blank record Bi to its Bfi state, and the and gate `618 setseach Di record leaving the circuit B1 to its Dti state.

What is claimed is:

1. A buffer system for the storage of a plurality of multibit binaryrecords of the data or blank type, each of said records including atwo-bit control field of which a first bit serves to identify the recordas a data or blank, said system including: a plurality of memoryelements through which the records are circulated on a serial bit-by-bitbasis and each of said memory elements having a capacity to holdpredetermined numbers of said records being circulated therethrough; acorresponding plurality of first control circuits respectively coupledto the inputs of said memory elements and serving to set the second bitof each of the aforesaid two-bit control fields to a predeterminedstatus for selected ones of the aforesaid records; a correspondingplurality of second control circuits respectively coupled to the outputsof said memory elements for detecting the status of the second bit ofeach of the two-bit control fields of the records output therefrom; anda plurality of exchange circuits interconnected with one another andinterposed between said second control circuits and said first controlcircuits and individually serving to transpose the position of a pair ofthe aforesaid records applied to its input terminals with respect to theposition thereof at its output terminals dependent upon the status ofsaid control fields of the said records as detected by said secondcontrol circuits.

2. The combination defined in claim 1, in which said first controlcircuits serve to set the second bit of each of the aforesaid two-bitcontrol fields to said predetermined status for the rst data record tobe circulated through any one of said memory elements.

3. The combination defined in claim 1, and which includes a blank inputline connected to an input of one of the said exchange circuits forintroducing said blank records into said system on a serial bit-by-bitsuccessive basis.

4. The combination defined in claim 1, and which includes a data inputline connected to an input of one of said exchange circuits for feedingrecords into the system on a serial bit-by-bit successive basis.

5. The combination defined in claim l, and which includes a data outputline connected to an output of one of said exchange circuits and onwhich the data records output from the system appear on a serialbit-by-bit successive basis.

6. The combination defined in claim 1, and which includes a blank inputline for introducing said blank records into said system on a serialbit-by-bit successive basis; a data input line for feeding the recordsinto the system on a serial bit-by-bit successive basis; and a dataoutput line on which the records output from the system appear on aserial bit-by-bit successive basis.

7. The combination defined in claim 6, in which said exchange circuitsinclude a plurality of first exchange circuits being seriallyinterconnected to one another and parallelly connected to the outputterminals of said second control circuits, and said data input linebeing connected to the first of said serially connected first exchangecircuits, and said exchange circuits further includes a plurality ofsecond exchange circuits like said first exchange circuits seriallyinterconnected to one another and parallelly connected to said firstexchange circuits and to the input terminals of said first controlcircuits, and said exchange circuits further includes an intermediateexchange circuit being serially interconnected between said first andsecond exchange circuits and being connected to said data output lineand to said blank output line.

8. The combination of claim 1, in which said memory elements have recordstoring capabilities in accordance with the progressions 1, 2, 4 2, 2n,2n1 1, where n is even.

9. The combination of claim 1, in which said memory elements have recordholding capabilities in accordance with the progressions 1, 2, 4 2'1-1,2, 2nl 1, where n is odd.

10. The combination defined in claim 1, in which said exchange circuitsinclude a plurality of first exchange circuits interconnected with oneanother and with the output terminals of said second control circuits,each of said first exchange circuits having two input terminals and twooutput terminals, and each of said first exchange circuits serving totranspose the position of a pair of records applied to said inputterminals with respect to the position thereof at said output terminalsdependent upon the status of said control fields of said records asdetected by said second control circuits; and a plurality of secondexchange circuits like said first exchange circuits and interconnectedwith one another and with said first exchange circuits, and said secondexchange circuits being further connected to the input terminals of saidfirst control circuits.

11. The combination defined in claim 6, in which said exchange circuitsinclude a plurality of first exchange circuits being seriallyinterconnected to one another and parallelly connected to the outputterminals of said second control circuits, said blank input line beingconnected to the first of said serially connected first exchangecircuits, and in which said exchange circuits further include aplurality of second exchange circuits like said first exchange circuitsserially interconnected to one another and parallelly connected to saidfirst exchange circuits and to the input terminals of said first controlcircuits, said data output line being connected to the first of saidserially connected second exchange circuits, and said exchange circuitsfurther include an intermediate exchange circuit being seriallyinterconnected between said first and second exchange circuits and beingconnected to said data input line.

No references cited.

PAUL I. HENON, Primary Examiner H. E. SPRINGBORN, Assistant Examiner

